The heterojunction tunnel triodes introduced by Jariwala and his colleagues could pave the way towards the realization of better performing low-power electronic devices. In principle, their design could also be scaled up to wafers, given that InSe-based 2D materials can be directly grown on silicon.
“In our next studies, we plan to scale up the material growth to make it more practical and scale down the device dimensions to improve the performance even further,” Jariwala added. “Demonstrating the material growth over a large area on a wafer will be a big milestone which we hope to achieve by next year.”
More information: Jinshui Miao et al, Heterojunction tunnel triodes based on two-dimensional metal selenide and three-dimensional silicon, Nature Electronics (2022). DOI: 10.1038/s41928-022-00849-0
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